1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically to a semiconductor device internally provided with a data bus.
2. Description of the Background Art
In a semiconductor device, the simplest method of transferring data from one functional block to another is to use one internal data bus for one bit of data, and to set that one internal data bus to the logic high or xe2x80x9cHxe2x80x9d level, or to the logic low or xe2x80x9cLxe2x80x9d level.
Such an internal data bus is herein referred to as a single data bus.
FIG. 11 is a diagram relating to a description of a single data bus in a conventional semiconductor device.
In FIG. 11, semiconductor device 701 includes an internal circuit 702 which is a first functional block, and an output circuit 704 which is a second functional block for receiving data from internal circuit 702 via a single data bus and for outputting the data to an external data bus 708.
Internal circuit 702 generates a data signal DATA internally and includes inverters 728 and 730 connected in series for amplifying data signal DATA and for outputting the amplified signal on the single data bus.
Output circuit 704 includes an inverter 748 for receiving and inverting a clock signal CLKO, a transmission gate 750 for taking in the data on the single bus according to clock signal CLKO and to an output from inverter 748, inverters 752 and 754 forming a latch circuit for latching the data taken in by transmission gate 750, an inverter 756 for receiving and inverting an output enable signal OE, and P-channel MOS transistors 758, 760 and N-channel MOS transistors 762, 764 connected in series between a power-supply node and a ground node.
P-channel MOS transistor 758 receives an output from inverter 756 at a gate. N-channel MOS transistor 764 receives output enable signal OE at a gate. Thus, P-channel MOS transistor 758 and N-channel MOS transistor 764 are activated when output enable signal OE is at the xe2x80x9cHxe2x80x9d level so that outputting of data becomes possible.
P-channel MOS transistor 760 and N-channel MOS transistor 762 receive an output from inverter 752 at the gates. The node connecting P-channel MOS transistor 760 and N-channel MOS transistor 762 forms an output node for output circuit 704, and is connected to external data bus 708. Other semiconductor devices 710 and 712 are connected to external data bus 708.
Semiconductor devices 710 and 712 include output circuits similar to that in semiconductor device 701, and the output nodes of these output circuits are connected to external data bus 708.
Generally, when a plurality of semiconductor devices share one external data bus as in FIG. 11, an output circuit is driven during the period in which data is effective and outputs the data to the external data bus, while the external data bus is cut off from output circuit during the period in which data is ineffective. The output circuit may be cut off from the external data bus by setting output enable signal OE to the xe2x80x9cLxe2x80x9d level.
FIG. 12 is an operational waveform chart for semiconductor device 701 shown in FIG. 11 when outputting data.
Referring to FIG. 12, let us consider the case in which internal circuit 702 outputs data signal DATA at time t1. The data signal transmitted via a single bus as far as the vicinity of output circuit 704 is referred to as DATAD. Due to propagation delay of data, at time t1, data signal DATAD has not yet been transmitted so that the data on the data bus is ineffective.
At time t2, data signal DATAD becomes effective. At time t3, clock signal CLKO and output enable signal OE, which serve as trigger signals to decide the timing at which data is output to the external data bus, are activated after data signal DATAD definitely attains the effective state, and thereafter, effective data is output on an external data bus EBUS.
If, for instance, clock signal CLKO and output enable signal OE are activated before time t2, ineffective data would be output on external data bus EBUS.
There also is, however, a potential problem, in avoiding outputting of ineffective data, that the timing for outputting data could be delayed if the timing at which clock signal CLKO and output enable signal OE are activated is held off too long after the time when data becomes definite at time t2.
This problem may be circumvented by the use of a complementary data bus.
FIG. 13 is a diagram related to a description of a complementary data bus.
As shown in FIG. 13, semiconductor device 801 includes an internal circuit 802 for internally generating and outputting complementary data signals DATA and ZDATA, a complementary data bus 806 for receiving outputs from internal circuit 802, and an output circuit 804 for receiving data from the complementary data bus and for outputting the received data to the outside.
Internal circuit 802 includes inverters 828 and 830 connected in series for outputting data signal DATA to the complementary data bus 806, and inverters 832 and 834 connected in series for receiving data signal ZDATA complementary to data signal DATA and for outputting the received data signal to complementary data bus 806.
Complementary data bus 806 includes a data bus line 806a for transmitting a data signal DATAD corresponding to data signal DATA to output circuit 804, and a data bus line 806b for transmitting a data signal ZDATAD corresponding to data signal ZDATA to output circuit 804.
Output circuit 804 includes an inverter 852 for receiving and inverting data signal DATAD, and a P-channel MOS transistor 860 and an N-channel MOS transistor 862 connected in series between a power-supply node and a ground node. A gate of P-channel MOS transistor 860 receives an output from inverter 852. A gate of N-channel MOS transistor 862 receives data signal ZDATAD. The node connecting P-channel MOS transistor 860 and N-channel MOS transistor 862 forms an output node for output circuit 804, and is connected to external data bus 808.
Other semiconductor devices 810 and 812 are connected to external data bus 808. Semiconductor devices 810 and 812 include output circuits similar to that in semiconductor device 804, and the output nodes of these output circuits are connected to external data bus 808.
FIG. 14 is an operational waveform chart related to a description of an operation of the complementary bus shown in FIG. 13.
Referring to FIGS. 13 and 14, data signals DATA and ZDATA are both at the xe2x80x9cLxe2x80x9d level before time t1. This state is the standby state of the complementary bus.
At time t1, one of data signals DATA and ZDATA attains the xe2x80x9cHxe2x80x9d level and the effective data is output.
At time t2, one of data signals DATAD and ZDATAD after the delay time caused by complementary data bus 806 attains the xe2x80x9cHxe2x80x9d level, and the effective data is propagated to output circuit 804. Accordingly, at time t3, one of P-channel MOS transistor 860 and N-channel MOS transistor 862 is rendered conductive, and the effective data is output to external data bus 808.
Since the standby state of the complementary bus is defined by the condition of both P-channel MOS transistor 860 and N-channel MOS transistor 862 being non-conductive, the transition of data from its ineffective state to the effective state triggers the outputting of the data to the external data bus. Therefore, when compared with the case of FIG. 12, the delay time between time t2 and time t3 is substantially eliminated and the period for which data is effective is fully utilized in the case of FIG. 14.
Next, let us consider a case in which the single data bus shown in FIG. 11 has a very heavy load capacitance.
FIG. 15 is an operational waveform chart of a case in which a single data bus has a heavy load capacitance.
As shown in FIGS. 11 and 15, the data of data signal DATA becomes effective at time t1. Since, however, the load capacitance of the single data bus is great, a very long transition period will be required before data signal DATAD on the data bus definitely attains the effective state.
Thus, clock signal CLKO and output enable signal OE must be activated at time t2 considerably delayed from time t1 to output the data to the external data bus. In other words, in order to ensure that effective data is taken in, clock signal CLKO must standby for a considerable length of time before the effective data appears on an internal data bus.
Even in such a case, the delay time may be shortened by the use of a complementary data bus and by an output circuit using a differential amplifier to amplify the potential difference between complementary data bus lines.
FIG. 16 is a simple representation of a configuration of a semiconductor device 901 in which an output circuit is provided with a differential amplifier.
As shown in FIG. 16, semiconductor device 901 includes an internal circuit 902 for generating and outputting complementary data signals DATA and ZDATA, a complementary data bus 906, and an output circuit 904.
Internal circuit 902 includes inverters 928 and 930 connected in series for transmitting data signal DATA to complementary data bus 906, and inverters 932 and 934 connected in series for transmitting data signal ZDATA to complementary data bus 906.
Output circuit 904 includes a differential amplifier 942 for amplifying the potential difference appearing on complementary data bus 906 and for outputting the amplified potential difference, an inverter 948 for receiving and inverting a clock signal CLKO, a transmission gate 950 for transmitting an output from differential amplifier 942 according to dock signal CLKO and to an output from inverter 948, inverters 952 and 954 forming a latch circuit for latching the output from differential amplifier 942 taken in by transmission gate 950, an inverter 956 for receiving and inverting an output enable signal OE, and P-channel MOS transistors 958, 960 and N-channel MOS transistors 962, 964 connected in series between a power-supply node and a ground node. N-channel MOS transistor 964 receives output enable signal OE at a gate. P-channel MOS transistor 958 receives an output from inverter 956 at a gate.
P-channel MOS transistor 960 and N-channel MOS transistor 962 both receive an output from inverter 952 at the gates. The node connecting N-channel MOS transistor 962 and P-channel MOS transistor 960 forms an output node for output circuit 904, and is connected to external data bus 908.
Other semiconductor devices 910 and 912 are connected to external data bus 908.
FIG. 17 is a circuit diagram showing a configuration of differential amplifier 942 shown in FIG. 16.
As shown in FIG. 17, differential amplifier 942 includes a gate circuit 972 for taking in the data transmitted via data bus lines 906a and 906b included in complementary data bus 906, an equaling circuit 974 for equalizing data bus lines 907a and 907b, and a sense amplifier circuit 976 for amplifying the potential difference appearing on data bus lines 907a and 907b. 
Gate circuit 972 includes an N-channel MOS transistor 978 connected between data bus lines 906a and 907a for receiving a control signal GATE at a gate, and an N-channel MOS transistor 980 connected between data bus lines 906b and 907b for receiving control signal GATE at a gate.
Equalizing circuit 974 includes an N-channel MOS transistor 982 connected between data bus line 907a and a ground node for receiving an equalizing signal EQ at a gate, and an N-channel MOS transistor 984 connected between data bus line 907b and the ground node for receiving equalizing signal EQ at a gate.
Sense amplifier circuit 976 includes an inverter 985 for receiving and inverting a control signal AMP, a P-channel MOS transistor 986 for receiving an output from inverter 985 at a gate and having a source connected to a power-supply node, an N-channel MOS transistor 988 for receiving control signal AMP at a gate and having a source connected to a ground node, a P-channel MOS transistor 990 and an N-channel MOS transistor 992 connected in series between a drain of P-channel MOS transistor 986 and a drain of N-channel MOS transistor 988 and both having a gate connected to data bus line 907b, and a P-channel MOS transistor 994 and an N-channel MOS transistor 996 connected in series between a drain of P-channel MOS transistor 986 and a drain of N-channel MOS transistor 988 and both having a gate connected to data bus line 907a. 
The node connecting P-channel MOS transistor 990 and N-channel MOS transistor 992 is connected to data bus line 907a. The node connecting P-channel MOS transistor 994 and N-channel MOS transistor 996 is connected to data bus line 907b. 
FIG. 18 is an operational waveform chart related to a description of an operation of the differential amplifier shown in FIG. 17.
Referring to FIGS. 17 and 18, at time t1, equalizing signal EQ falls to the xe2x80x9cLxe2x80x9d level, control signal GATE is activated, and the potential difference generated by data transmitted via data bus lines 906a and 906b appears on data bus lines 907a and 907b. 
At time t2, control signal GATE falls to the xe2x80x9cLxe2x80x9d level. Then, control signal AMP rises to the xe2x80x9cHxe2x80x9d level, and sense amplifier circuit 976 is activated. Accordingly, the potential difference between data bus lines 907a and 907b is magnified, and the amplitudes of data signals DATAD and ZDATAD are amplified. Thus, data is output to the outside.
At time t3, control signal AMP falls to the xe2x80x9cLxe2x80x9d level, the equalizing signal once again is activated to the xe2x80x9cHxe2x80x9d level, and the differential amplifier enters the standby state.
FIG. 19 is an operational waveform chart showing how data is transmitted in semiconductor device 901 shown in FIG. 16.
Referring to FIGS. 16 and 19, the effective data is output from internal circuit 902 at time t1.
At time t2, data is transmitted via complementary data bus 906 as far as to differential amplifier 942. At time t3, the potential difference appearing on the complementary data bus is magnified by the operation of differential amplifier 942. Then at time t4, the effective data amplified by differential amplifier 942 is taken into a section in the output circuit, and the data is output to the external data bus.
At time t5, the equalizing signal within differential amplifier 942 is activated, and at time t6, differential amplifier 942 once again enters the standby state.
As described above, even in view of the disadvantage of increased surface area due to an increase in the number of interconnection lines, a complementary data bus would be employed if the advantages of using the complementary data bus prevail.
It might be noted, however, in respect of data transfer speed, the complementary data bus is not always absolutely advantageous.
FIG. 20 is a diagram showing a comparison of data transfers using a single data bus and a complementary data bus.
In the case of data transfer via the complementary data bus, the access time, or the period of time required from the time when data is output from an internal circuit and the data transfer begins to the time when data is output to the outside, is short. In contrast, the access time is long with a single data bus since a differential amplifier or the like is not provided. Thus, the cycle in which data is transmitted can also be made shorter with the complementary data bus.
When the same number of interconnection lines are used, however, the single data buses can transfer twice as much data as the complementary buses. Therefore, much use can be expected of the single data bus even with its accompanying disadvantages of somewhat lowered transfer frequency and a slight reduction in the access speed.
It is of great importance, therefore, to implement either the function of a semiconductor device having complementary data buses for transferring n bits of data or the function of a semiconductor device having single data buses for transferring 2n bits of data in the same chip by the switching of a control signal, or to do so with master slices by changing the masks used when forming a metal interconnection layer.
One object of the present invention is to provide a semiconductor device that allows data buses that are internally provided to be switchably used either as complementary data buses for transmitting n bits or as single data buses for transmitting 2n bits according to the intended use.
The present invention is a semiconductor device provided with an internal circuit, first and second data bus lines, and an output circuit. The internal circuit includes a data output portion for outputting a first data signal, a second data signal, and a third data signal complementary to the first data signal, and a first switching circuit for outputting one of the second data signal and the third data signal. The first data bus line receives the first data signal. The second data bus line receives an output from the first switching circuit. The output circuit outputs to the outside a signal corresponding to data transmitted via the first data bus line and the second data bus line. The output circuit includes a first output buffer circuit for outputting a first output signal corresponding to the first data signal, and a second output buffer circuit which outputs a second output signal corresponding to the second data signal when the first switching circuit outputs the second data signal, and which is rendered non-active when the first switching circuit outputs the third data signal.
Thus, the main advantage of the present invention is that one chip of semiconductor memory device can be made to perform a variety of operations owing to the fact that a data bus internally provided can be switchably used either as a data bus for transmitting complementary data or as a data bus for transmitting single data.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.